View STP08CDC596TTR_1318824.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

STP08CDC596
8-BIT CONSTANT CURRENT LED SINK DRIVER WITH FULL OUTPUT DETECTION

8 CONSTANT CURRENT OUTPUT CHANNELS ADJUSTABLE OUTPUT CURRENT THROUGH ONE EXTERNAL RESISTOR OPEN AND SHORT LINE, SHORT TO GND, SHORT TO V-LED SUPPLY ERROR DETECTION SERIAL DATA IN/PARALLEL DATA OUT SERIAL OUT CHANGE STATE ON THE FALLING EDGES OF CLOCK OUTPUT CURRENT: 20-120 mA 25 MHz CLOCK FREQ.
DIP-16
SO-16
DESCRIPTION The STP08CDC596 is a monolithic, medium-voltage, low current power 8-bit shift register designed for LED panel display. The STP08CDC596 contains a 8-bit serial-in, parallel-out shift register that feeds a 8-bitD-type storage register. In the output stage, eight regulated current sources were designed to provide 15-120mA constant current to drive the LEDs. The STP08CDC596 contains the built-IN error detection feature. The device performs this additional function without any increase of the pin number and any change of the pin function, if compared to the standard device without error detection. Consequently, choosing this device does not mean to change the footprint on the board. To perform this functionality mode, the device needs a digital key coming from the Microprocessor. The STP08CDC596 is able to detect: open and short on the LED line, short to Table 1: Order Codes
Type STP08CDC596B1 STP08CDC596M STP08CDC596MTR STP08CDC596TTR Temp. Range -40C to -40C to -40C to -40C to 125C 125C 125C 125C
TSSOP16
GND, short to Led voltage supply. The data mapping of output channels status detection is provided by a feedback from the serial output to the Microprocessor. Trough an external resistor, users may adjust the STP08CDC596 output current, controlling the light intensity of LEDs. The STP08CDC596 guarantees 16V output driving capability, allowing users to connect more LEDs in series. The high clock frequency, 25 MHz, also satisfies the system requirement of high volume data transmission. The device is offered in DIP-16, SO-16 and TSSOP-16 packages. The STP08CDC596 is well suitable for traffic display signs where the detection feature is strongly required.
Package DIP-16 SO-16 (Tube) SO-16 (Tape & Reel) TSSOP16 (Tape & Reel)
Comments 25 part per tube 50 parts per tube 2500 parts per reel 2500 parts per reel
October 2005
Rev. 2
1/20
STP08CDC596
Table 2: Current Accuracy
Current accuracy Output Voltage Between bits 0.7V TYP. 3% Between ICs 10% 20 to 120 mA Output Current
Figure 1: Pin Connection
Table 3: Pin Description
PIN N 1 2 3 4 5-12 13 14 15 16 Symbol GND SDI CLK LE/DM1 OUT 0-7 OE/DM2 SDO R-EXT VDD Name and Function Ground Terminal Serial data input terminal Clock input terminal Latch input terminal Output terminal Output enable input terminal (active low) Serial data out terminal Constant Current programming 5V Supply voltage terminal
Table 4: Absolute Maximum Ratings
Symbol VDD VO IO VI IGND fCLK TOPR TSTG Supply Voltage Output Voltage Output Current Input Voltage GND Terminal Current Clock Frequency Operating Temperature Range Storage Temperature Range Parameter Value 0 to 7 -0.5 to 16 120 -0.4 to VDD+0.4 980 25 -40 to +125 -55 to +150 Unit V V mA V mA MHz C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
2/20
STP08CDC596
Table 5: Thermal Data
Symbol Rthj-amb Parameter Thermal Resistance Junction-ambient DIP-16 90 SO-16 125 TSSOP16 140 Unit C/W
Table 6: Recommended Operating Conditions
Symbol VDD VO IO IOH IOL VIH VIL twLAT twCLK twEN tHOLD(D) fCLK Parameter Supply Voltage Output Voltage Output Current Output Current Output Current Input Voltage Input Voltage LE/DM1 Pulse Width CLK Pulse Width OE/DM2 Pulse Width (1) Hold Time for DATA Clock Frequency (2) VDD = 3.0 to 3.6V OUTn SERIAL-OUT SERIAL-OUT 0.7VDD -0.3 10 10 120 5 4 8 15 Test Conditions Min. 3.3 Typ. Max. 5.5 16.0 120 +1 -1 VDD+0.3 0.3VDD 20 20 400 20 15 15 25 Unit V V mA mA mA V V ns ns ns ns ns ns MHz
tSETUP(D) Setup Time for DATA tSETUP(L) Setup Time for LATCH
(1) If the device is connected in cascade, it may not be possible achieve the maximum data transfer. Please considered the timings carefully. (2) In normal mode the OE/DM2 must remain low at least two clock cycles.
Table 7: Electrical Characteristics (VDD=5V, T = 25C, unless otherwise specified.)
Symbol VIH VIL IOH VOL VOH IOL1 IOL2 IOL1 IOL2 RSIN(up) Output Current Error between bit (All Output ON) Pull-up Resistor REXT = OPEN REXT = 910 REXT = 360 Supply Current (ON) REXT = 910 REXT = 360 OUT 0 to 7 = OFF OUT 0 to 7 = OFF OUT 0 to 7 = OFF OUT 0 to 7 = ON OUT 0 to 7 = ON Parameter Input Voltage High Level Input Voltage Low Level Output Leakage Current VOH = 16 V VDD-0.4V 18.8 46.00 20.9 51.5 2 1 150 100 300 200 0.45 3.0 8.2 3.1 8.4 24.00 56.5 5 4 600 400 0.7 6.0 12.0 6.2 12.8 Output Voltage (Serial-OUT) IOL = 1mA Output Voltage (Serial-OUT) IOH = -1mA Output Current VO = 0.7V REXT = 910 VO = 0.7V REXT = 360 VO = 0.7V REXT = 910 VO = 0.7V REXT = 360 Test Conditions Min. 0.7VDD GND Typ. Max. VDD 0.3VDD 10 0.4 Unit V V A V V mA mA % % K K mA
RSIN(down) Pull-down Resistor IDD(OFF1) Supply Current (OFF) IDD(OFF2) IDD(OFF3) IDD(ON1) IDD(ON2)
3/20
STP08CDC596
Table 8: Switching Characteristics (VDD=3.3 to 5.5V, T = 25C, unless otherwise specified.)
Symbol tPLH1 Parameter Propagation Delay Time, CLK-OUTn, LE/DM1 = H, OE/DM2 = L Propagation Delay Time, LE/DM1-OUTn, OE/DM2 = Propagation Delay Time, OE/DM2-OUTn, LE/DM1 = Propagation Delay Time, CLK-SDO Propagation Delay Time, CLK-OUTn, LE/DM1 = H, OE/DM2 = L Propagation Delay Time, LE/DM1-OUTn, OE/DM2 = Propagation Delay Time, OE/DM2-OUTn, LE/DM1 = Propagation Delay Time, CLK-SDO Output Rise Time Output Fall Time Test Conditions VDD = 3 V VIL = GND IO = 40mA L H 25 30 35 60 ns ns REXT = 470 VIH = VDD CL = 13pF VL = 3 V RL = 65 150 140 280 280 ns ns Min. Typ. 180 Max. 280 Unit ns
tPLH2 tPLH3 tPLH tPHL1
tPHL2 tPHL3 tPHL tr tf
30 L 35 H 30 220 20
50 70 40
ns ns ns ns ns
EQUIVALENT CIRCUIT OF INPUTS AND OUTPUTS Figure 2: OE/DM2 Terminal
4/20
STP08CDC596
Figure 3: LE/DM1 Terminal
Figure 4: CLK, SDI Terminal
Figure 5: SDO Terminal
5/20
STP08CDC596
Figure 6: Block Diagram
Figure 7: Timing Diagram
In normal mode the OE/DM2 must remain low at least two clock cycles.
6/20
STP08CDC596
Figure 8: Clock, Serial-In, Serial-Out
Figure 9: Clock, Serial-In, Latch, Enable, Outputs
7/20
STP08CDC596
Figure 10: Outputs
TEST CIRCUIT Figure 11: DC Characteristic
Figure 12: AC Characteristic
8/20
STP08CDC596
RUNNING THE DETECTION MODE Phase One: "Entering In Detection Mode" From the "Normal Mode" condition the device can switch to the "Error Detection Mode" by a logic Table 9: Entering In Detection Truth Table
CLK OE/DM2 LE/DM1 1 H L 2 L L 3 H L 4 H H 5 H L
sequence on the OE/DM2 and LE/DM1 pins as showed in the following Table and Diagram:
Figure 13: Entering In Detection Timing Diagram
After these five CLK cycles the device goes into the" Error Detection Mode" and at the 6th rise front of CLK the SDI data are ready for the sampling. Phase Two: "Error Detection" The eight data bits must be set "1" in order to set ON all the outputs during the detection. The data are latched by LE/DM1 and after that the outputs are ready for the detection process. When the Figure 14: Detection Diagram
Micro controller switches the OE/DM2 to LOW, the device drives the LEDs in order to analyze if an OPEN or SHORT condition has occurred.
9/20
STP08CDC596
The LEDs status will be detected al least in 2 microseconds and after this time the micro controller puts OE in HIGH state and the output data detection result will go to the microprocessor via SDO. The detection data format is the same of data in normal mode. As soon as all the detection data bits are available on the serial line, the device may go back to normal mode operation.
CONDITIONS IN ORDER TO GET A SUCCESSFULLY DETECTION CONDITION Table 10: Detection Condition (VDD = 3.3 to 5 V Temp. Range -40 to 85C)
SW-1 or SW-3b Open Line or Output Short ==> IODEC 0.5 x IO to GND detected Short on LED or Short to ==> VO 2.4 V SW-2 or SW-3a V-LED detected No error detected No error detected ==> IODEC 0.5 x IO ==> VO 2.2 V
where: IO = the output current programmed by the REXT, IODEC = the detected output current in detection mode.
Figure 15: Detection Mode
10/20
STP08CDC596
Phase Three: "Resuming to Normal Mode" The sequence for re-entering in normal mode is showed in the following Table and diagram: Table 11: Resuming to Normal Mode Timing Diagram
CLK OE/DM2 LE/DM1 1 H L 2 L L 3 H L 4 H L 5 H L
Figure 16: Resuming to Normal Mode Timing Diagram
For proper device operation the "Entering in detection" sequence must be follow by a "Resume Mode" sequence, isn't possible to insert consecutive equal sequence.
11/20
STP08CDC596
Figure 17: Typical Output Current-REXT Resistor Figure 19: Typical Dropout Voltage vs Output Current
Figure 18: Power Dissipation vs Temperature Package
Figure 20: Typical Output Current vs IOL(%)
12/20
STP08CDC596
Figure 21: Timing example for Open and/or Short detection
13/20
STP08CDC596
Plastic DIP-16 (0.25) MECHANICAL DATA
mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch
P001C
14/20
STP08CDC596
SO-16 MECHANICAL DATA
DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.25 1.64 0.46 0.25 0.013 0.007 0.019 0.004 MIN. inch TYP. MAX. 0.068 0.010 0.063 0.018 0.010
0016020D
15/20
STP08CDC596
TSSOP16 MECHANICAL DATA
mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0 0.45 0.60 0.05 0.8 0.19 0.09 4.9 6.2 4.3 5 6.4 4.4 0.65 BSC 8 0.75 0 0.018 0.024 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 5.1 6.6 4.48 0.002 0.031 0.007 0.004 0.193 0.244 0.169 0.197 0.252 0.173 0.0256 BSC 8 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0079 0.201 0.260 0.176 inch
A
A2 A1 b e K c L E
D
E1
PIN 1 IDENTIFICATION
1
0080338D
16/20
STP08CDC596
Tape & Reel SO-16 MECHANICAL DATA
mm. DIM. MIN. A C D N T Ao Bo Ko Po P 6.45 10.3 2.1 3.9 7.9 12.8 20.2 60 22.4 6.65 10.5 2.3 4.1 8.1 0.254 0.406 0.082 0.153 0.311 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 0.262 0.414 0.090 0.161 0.319 MIN. TYP. MAX. 12.992 0.519 inch
17/20
STP08CDC596
Tape & Reel TSSOP16 MECHANICAL DATA
mm. DIM. MIN. A C D N T Ao Bo Ko Po P 6.7 5.3 1.6 3.9 7.9 12.8 20.2 60 22.4 6.9 5.5 1.8 4.1 8.1 0.264 0.209 0.063 0.153 0.311 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 0.272 0.217 0.071 0.161 0.319 MIN. TYP. MAX. 12.992 0.519 inch
18/20
STP08CDC596
Table 12: Revision History
Date 15-Jun-2005 11-Oct-2005 Revision 1 2 First Release. Minor Revision Description of Changes
19/20
STP08CDC596
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2005 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
20/20

▲Up To Search▲

Price & Availability of STP08CDC596TTR

	To Download STP08CDC596TTR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .